Today's complex digital systems contain storage devices, finite-state machines, and other such structures which control the movement of information by various clocking methods. Conversely, combinatorial logic devices, which are usually asynchronous, do not require time-based control signals for their operation. The output of an ideal combinatorial logic circuit is completely defined at any time by its inputs. In many digital circuits, however, it is expedient to cause the circuit's output to depend on both present and past inputs. Digital circuits whose outputs depend on such inputs are known as sequential circuits. A subset of this type of circuit is the synchronous sequential circuit, which requires a control signal to mark the passage of time and thereby delineate present inputs from past inputs. A clock signal serves this purpose, thereby controlling the transfer of digital information from one storage location to another.
An ideal clock signal is simply a periodic alternation between a logic high level and a logic low level. Typically, today's logic circuits use multi-phase clocks. Such clocking schemes may employ two-phase or four-phase clocks, or may use an even greater number of phases. The various phases are normally non-overlapping to prevent, as much as possible, race conditions and hazards, which commonly occur in digital circuits.
A hazard occurs when a circuit, under normal operating conditions, has the possibility of generating positive or negative pulses of possibly undefined duration at its output, when no such transitions should occur. This might occur, for example, where a designer fails to properly reduce logic terms. A race condition, on the other hand occurs when the output of a circuit is determined in part by which of two or more rising or falling edges is first received as an input to the circuit. Such a situation is normally avoided by synchronizing signals to a clock signal, meaning that the signals are related to the clock signal (and each other) in such a way that those signals may safely drive a circuit clocked by that clock signal. Such a race condition may result in a runt pulse at the circuit's output if no steps are taken to avoid it. Because a well-defined timing relationship is unlikely to exist between such input signals, neither the duration nor amplitude of a runt pulse is defined. One possible source of races is the improper distribution of clocking signals because the timing relationships involved become undefined.
Because modern digital systems are often very large, the number of devices driven by a clock may exceed the drive capabilities of the clock generation circuits, a common occurrence. In such a case, a clock signal will be distributed using one or more driver circuits because the clock circuit is unable to drive all of the devices directly. When using multiple clock drivers, the circuits being driven will be partitioned into logical subcircuits and the output of each clock driver used to drive those subcircuits. The signal propagation delays through each of the clock driver circuits will likely differ. The load presented to each drive circuit will also likely differ, also causing differences in the outputs of each clock driver circuit. These differences are known as clock skew.
Generally speaking, information transfer from a signal synchronized to a later clock to circuit elements clocked with an earlier clock will function correctly. However, a transfer of information from an earlier clock to a later clock may encounter problems. For example, if two flip-flops are connected serially with the first flip-flop providing input to the second flip-flop, the circuit should function as a shift register. If two separate clocks are provided, one to each flip-flop, and the second flip-flop is clocked simultaneously with or before the first flip-flop, both flip-flops may be loaded with the same data, and thus fail to function as a shift register. In such cases, the two clocks must be synchronized in some way.
Similarly, outputs from a first digital circuit operating using a first clock which are taken as input by a second digital circuit operating on a second clock must often be synchronized to the second clock. This is also true of asynchronous inputs generated by a user, sensors, or other such input sources.
FIG. 1 illustrates several of the proceeding concepts. FIG. 1 shows a clock enable signal rclk_en 100 generated by a control signal receiver 102 from a bus control input 104 (received from a bus (not shown)). Clock enable signal rclk_en 100 enables the generation of a clock rclk 110. A bus clock 112 is also received from the bus. Bus clock 112 is provided to a phase detector 114 and a delay-locked loop 116. Phase detector 114 compares bus clock 112 with a clock mclk 120, which also clocks control signal receiver 102. Phase detector 114 generates a phase difference signal 122 that represents the difference in phase between bus clock 112 and mclk 120. Delay-locked loop 116 generates a master clock dllclk 130 by variably delaying bus clock 112. Delay-locked loop 116 uses phase difference signal 122 to set the amount of delay necessary to keep mclk 120 synchronous with bus clock 112.
The circuit of FIG. 1 operates in the following manner. Clock dllclk 130 is fed into a inverter 132 which drives a first NAND gate 134 and a second NAND gate 136. The second input of first NAND gate 134 is tied high to voltage V.sub.DD 160, causing the output of first NAND gate 134 to follow the input of inverter 132. First NAND gate 134 outputs a delayed version of dllclk 130, which then passes through an inverter string 140 and emerges as mclk 120. Similarly, second NAND gate 136 drives an inverter string 150 and emerges as rclk 110. Inverter string 150 serves as a clock driver circuit, allowing rclk 110 to drive large numbers of devices.
The function of second NAND gate 136 is to disable rclk 110. The function of first NAND gate 134 is to maintain equality in the delays experienced in generating rclk 110 and mclk 120. Because the delay experienced in generating rclk 110 from dllclk 130 is equal to that experienced in generating mclk 120 from dllclk 130, rclk 110 is synchronous with mclk 120, save for the fact that rclk 110 is not generated until enabled by rclk_en 100. So long as the delays in generating rclk 110 and mclk 120 are kept equal, other devices may therefore be used in place of first NAND gate 134 and second NAND gate 136, such as NOR gates or tristable devices. However, the delays experienced in generating rclk 110 from dllclk 130 should always be identical to those experienced in generating mclk 120. Because the phase delay experienced in generating mclk 120 from dllclk 130 is defined (i.e., the delay is calculable and/or measurable, although it may not be known), a substantially quantifiable phase relationship exists between mclk 120 and dllclk 130. An example of a delay-locked loop receiver is described in U.S. patent application Ser. No. 08/795,657 filed Feb. 6, 1997 entitled "DELAY LOCKED LOOP CIRCUITRY FOR CLOCK DELAY ADJUSTMENT," having as inventors Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark Johnson, Benedict Lau, Leung Yu, Bruno W. Garlepp, Yiu-Fai Chan, Jun Kim, Chanh Vi Tran, and Donald Stark, and assigned to Rambus, Inc., the assignee of the present invention, and is hereby incorporated by reference in its entirety.
FIG. 2A illustrates the waveforms which may be generated by the operation of the circuit illustrated in FIG. 1. Throughout this discussion, references to a signal or element of a preceding figure will use the original reference numbers. Moreover, idealized signal waveforms will be used to simplify the discussion. As illustrated in FIG. 2A, the waveform of dllclk 130 is a square wave having a 50% duty cycle and a period of (T.sub.3 -T.sub.0). As is shown in FIG. 2A, rclk 110 and mclk 120 of FIG. 1 are simply delayed versions of dllclk 130, assuming the circuit is operating under nominal conditions and, with regard to rclk 110, rclk_en 100 is active. These nominal signals are indicated by traces rclk_nom 202 and mclk_nom 204.
However, the delay experienced between dllclk 130 and the outputs of the circuit in FIG. 1 are affected by variables such as temperature, supply voltage, process parameters, and other such variables. For example, at a low operating temperature with a high supply voltage and a fast process, the circuit of FIG. 1 provides a relatively short delay, as indicated by a trace r/mclk_fast 210. Trace r/mclk_fast 210 experiences a delay of (T.sub.1 -T.sub.0), as indicated by a transition 211.
Alternatively, a low supply voltage, high operating temperature, and slow process significantly increase the delay experienced. Such a situation is shown in FIG. 2A by a trace r/mclk_slow 215, which experiences a delay of (T.sub.4 -T.sub.0), as indicated by a transition 216. Variations in process parameters may also alter the delay provided by the circuit in FIG. 1, making the delay longer or shorter depending on the parameter and the manner in which it is varied. Thus, the phase relationship between dllclk 130 and either of rclk 110 or mclk 120 is an arbitrary (although measurable) one, due to the dependence on loading, process, voltage, temperatures, and other factors. Any of these conditions can lead to errors in the generation of rclk 110 using circuits of the prior art.
In operation, the circuit of FIG. 1 generates rclk 110 and mclk 120 in a manner which keeps rclk 110 and mclk 120 substantially in phase. This is done through careful circuit design, taking into consideration the loads driven by these clock signals, the proportions of the inverters in inverter strings 140 and 150, NAND gates 134 and 136, the physical layout of these elements, and other considerations.
FIGS. 2B, 2C, and 2D are phase diagrams corresponding to the various traces of FIG. 2A. FIG. 2B illustrates the nominal phase delay represented by rclk_nom 202 and mclk_nom 204. Clock dllclk 130 is shown as a vector 220 having a phase of 0.degree.. Clocks rclk_nom 202 and mclk_nom 204, which are synchronized, are shown as a vector 221. Vector 221 lags vector 220 by about 180.degree.. In these figures, the delay experienced between dllclk 130 and rclk_nom 202/mclk_nom 204 is given by: ##EQU1##
where T.sub.Delay is the delay experienced, .phi. is the phase difference, and T.sub.dllclk 130 is the period of dllclk 130. Thus, vector 221 lags vector 220 by 0.5 T.sub.dllclk 130, which is shown in FIG. 2B as a period of T.sub.Delay 222. This period is equal to the time (T.sub.2 -T.sub.0) in FIG. 2A.
In FIG. 2A, dllclk 130 is active from 0.degree. to 180.degree. and inactive from 180.degree. to 360.degree. (i.e., 0.degree.). As will be discussed in detail with regard to FIG. 2E, rclk_nom 202 can safely be synchronized by the circuit of FIG. 1 when dllclk 130 is inactive (i.e., between 180.degree. and 360.degree.). This synchronization point is nominally at a point in the center of the inactive phase of dllclk 130 (i.e., at a phase angle of about 270.degree.).
FIGS. 2C and 2D illustrate the cases shown in FIG. 2A as r/mclk_fast 210 and r/mclk_slow 215, respectively. In both of these figures, dllclk 130 is again shown as a vector 220. Clock r/mclk_fast 210 is shown as a vector 223 in FIG. 2C. Vector 223 lags vector 220 by only about 45.degree. due to the environmental and process factors previously discussed. This translates to about 0.125 T.sub.dllclk 130, which is shown in FIG. 2C as a period of T.sub.Delay 226. This period is equal to the time (T.sub.1 -T.sub.0) in FIG. 2A.
FIG. 2D shows clock r/mclk_slow 210 as a vector 225. Vector 225 lags vector 220 by a large amount, about 382.degree., again due to the environmental and process factors previously discussed. This translates to about 1.06 T.sub.dllclk 130, which is shown in FIG. 2C as a period of T.sub.Delay 224. This period is equal to the time (T.sub.4 -T.sub.0) in FIG. 2A.
FIG. 2E shows the preferred timing relationship between rclk_en 100 and dllclk 130. Preferably, rclk_en 100 goes active (in this case, high) at a time T.sub.0 when dllclk 130 is inactive (i.e., low), thereby allowing dllclk 130 to propagate through inverter 132, NAND gate 136, and inverter string 150, thereby providing a delayed version of itself, rclk 110. The delay experience by dllclk 130 is indicated in FIG. 2E by a transition 230 having a duration (T.sub.2 -T.sub.1).
Unfortunately, as illustrated in FIG. 2F, simply allowing rclk_en 100 to become active at any point in time can cause the generation of runt pulses. In FIG. 2F, rclk_en 100 goes active (i.e., high) at a time T.sub.0, which is during a period when dllclk 130 is also active (i.e., high). Because the circuit in FIG. 1 is simply a combinatorial circuit, rclk 110 will go high any time rclk_en 100 and dllclk 130 are both high, albeit at a later time due to delay within the circuit. This being the case, a race condition exists and, in this case, produces a runt pulse 235. The leading edge of runt pulse 235 is related to rclk_en 100 as indicated by a transition 240. The delay between these two edges is (T.sub.0 -T.sub.2), and is equal to the delay experienced between dllclk 130 and rclk 110 (T.sub.5 -T.sub.4) as indicated by a transition 245. The falling edge of runt pulse 235 occurs at a time T.sub.3 and corresponds to the falling edge of dllclk 130 occurring at T.sub.1.
Runt pulse 235, having indeterminate amplitude and duration, is undesirable because it may cause intermittent failures, depending on the timing of the asynchronous input and the nature of the clocked circuit. Such effects can include the failure to meet the timing constraints of the circuits driven by the clock, the generation of metastable states in bistable devices, certain of the driven circuits being out of synchronization with other portions thereof, and other undesirable effects.
A common solution to such problems is the inclusion of a latch or flip-flop to gate the offending control signal. FIG. 3 illustrates such a solution. A latch 300 is used to synchronize rclk_en 100 with dllclk 130. Clock enable rclk_en 100 is gated by latch 300, thereby generating a gated version of rclk_en 100, a clock enable signal g_rclk_en 310, which is provided to second NAND gate 136. In using a flip-flop to gate the input, g_rclk_en 310 is prohibited from enabling the output of rclk 110 until a time at which dllclk 130 is active. The waveforms generated using this common solution are illustrated in FIGS. 4A, 4B, and 4C.
FIG. 4A illustrates the case where rclk_en 100 goes high at a time T.sub.O 700 when dllclk 130 is low. As was illustrated in FIG. 2E, this situation would not even cause problems for the circuit illustrated in FIG. 1. In the circuit illustrated in FIG. 3, this situation is also handled correctly. In FIG. 4A, rclk_en 100 goes high at a time T.sub.0, but must wait for the next rising edge of dllclk 130. This occurs at a time T.sub.1, as indicated by a transition 400. At time T.sub.1, the rising edge of dllclk 130 clocks the active state of rclk_en 100 into latch 300, thereby causing a rising edge on the output of latch 300. This is illustrated in FIG. 4A as the rising edge in g_rclk_en 310 at time T.sub.1, and is indicated by a transition 405. For simplicity, this timing relationship is shown in FIG. 4A as being instantaneous; in an actual circuit, there would be some delay associated with transition 405 which might delay g_rclk_en 310 going active by one cycle of dllclk 310.
At this point, propagation of dllclk 130 through inverter string 150 is enabled and dllclk 130 is propagated, appearing as rclk 110 at a time T.sub.2, which is indicated by a transition 420. The duration of this transition is equivalent to the delay experienced by dllclk 130 propagating through inverter string 150 when generating rclk 110.
FIG. 4B illustrates the anomalous situation shown in FIG. 2F. However, instead of generating a runt pulse like the one shown in FIG. 2F, the circuit of FIG. 3 effectively delays the application of g_rclk_en 310 to second NAND gate 136 until such time as dllclk 130 transitions to an active state. As shown in FIG. 4B, rclk_en 100 becomes active at a time T.sub.3, which is at a time when dllclk 130 is also active. Without latch 300, a runt pulse such as that exhibited by the circuit of FIG. 1 would be generated. However, rclk_en 100 is not applied directly to second NAND gate 136, but is gated through latch 300 by dllclk 130. This dependency is indicated in FIG. 4B by a transition 425. When dllclk 130 becomes active at a time T.sub.4, rclk_en 100 is already active. This is propagated through latch 300, causing g_rclk_en 310 to also become active. This transition is indicated by a transition 430, which again is shown as being instantaneous for the sake of simplicity. A pulse 435 of dllclk 130 then propagates through inverter string 150 and emerges as a pulse 440 of rclk 110, as before. This occurs at a time T.sub.5. The delay between pulse 435 (enabled by g_rclk_en 310) and pulse 440 is indicated by a transition 445 which is equal in duration to the delay experienced by pulse 435 (T.sub.5 -T.sub.4).
However, the solution provided by the circuit illustrated in FIG. 3 is not without its own problems. Any bistable device (i.e., circuits containing flip-flops, latches, or other switching circuits) may suffer from what is known as metastability, under the proper input conditions.
Normally, digital logic has two stable states which are a function of the steady-state transfer functions of the elements of which they consist. However, a third equilibrium point exists in these transfer functions. This is known as the metastable state and occurs somewhere near the half-way point between the voltage levels representing a logic 0 and a logic 1. However, this is not a truly stable operating point because random noise will tend to drive a circuit operating at this point towards one of the stable operating points (i.e., a logic 0 or logic 1). Additionally, this metastable state lasts for a non-deterministic period of time, creating the possibility that circuits driven by elements in this state may find themselves in unknown states for an indeterminate time and almost assuredly out of synchronization once the metastability has resolved.
Such a phenomena is illustrated by the traces in FIG. 4C. In FIG. 4C, rclk_en 100 is applied even later than in FIGS. 4A and 4B, at a time T.sub.6. However, also occurring at time T.sub.6 is a rising edge of dllclk 130. This results in a race condition. Because they occur at substantially the same instant (i.e., at a time which violates the setup and hold times of latch 300), the output of latch 300, g_rclk_en 310, is put into a metastable state. This condition is indicated by transitions 450 and 455, which indicate that both rclk_en 100 and dllclk 130 are driving the transition which is supposed to occur in g_rclk_en 310. The metastable state of g_rclk_en 310 resolves to a high level within some indeterminate time (as shown in FIG. 4C). This then drives rclk_glitch 475, as indicated by a transition 470. Clock rclk_glitch 475 may then operate normally, but will likely reflect a delayed version of the glitches caused by the metastability of g_rclk_en 310, in the form of runt pulses. The latter situation is indicated by a runt pulse 475, which occurs at a time T.sub.7. If this occurred, synchronization in the circuits driven by rclk_glitch 475 would likely be lost, resulting in improper operation of those circuits.
While this type of problem can be addressed to some extent by changes in design, it is impossible to eliminate. The measure of the frequency with which such a failure could be expected to occur is known as the mean time between failures (MTBF). However, this figure is difficult to calculate and changes with variations in the process used to fabricate the device and operating conditions such as temperature and supply voltage. Moreover, the possibility of failure is not eliminated by the use of such analytical methods.
What is therefore required is a circuit architecture which removes the possibility of the runt pulses created by the circuit of FIG. 1 and the occasional metastability experienced by the circuit of FIG. 3. In other words, such a circuit should have no probability of failure resulting from the gating of the clock. Such a circuit should allow the synchronization of an enable signal such as rclk_en 100 with a clock signal such as dllclk 130 with minimum latency, and insensitivity to process variations and environmental parameters such as temperature and supply voltage.